CASA 2014 Abstracts and Bios

Rajesh Gupta
University of California, San Diego

Morning Keynote: Managing Uncertainty Through Adaptation in Computing and Memory Systems

Uncertainty in computing has grown from a performance characterization challenge to a major reliability headache. Small parametric variations in manufacturing or operating conditions are amplified into major timing and performance effects across manufactured parts. Hardware designers have run out of room in sandbagging designs with ever expanding guardbands. These developments have nearly flattened the very scaling curve that made microelectronics so attractive. This talk explores growing trends towards use of sensing of the ongoing computation, system state and its physical environment for important data to adapt system at different levels. In this talk, I will discuss our experiments to characterize variability, program structuring and task scheduling that can make a software stack robust against variations in the computing environment and how it connects to approximations in computing results through relaxed acceptance criteria in applications. This talk represents part of the effort at NSF Expeditions in Computing program on Variability.

Rajesh K. Gupta is a professor and chair of Computer Science and Engineering department at UC San Diego. His research focus is on energy efficiency from algorithms, devices to systems that scale from IC chips, data centers to commercial buildings. His ongoing projects are focused on mitigating microelectronic variability and creating non-volatile storage/memory systems. Gupta received a BTech in EE from IIT Kanpur, MS in EECS from UC Berkeley and a PhD in Electrical Engineering from Stanford University. Gupta is a Fellow of the IEEE.

Sanjit Seshia
University of California, Berkeley

Afternoon Keynote: A Formalization and Evaluation of Timing Repeatability

Sanjit A. Seshia is an Associate Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received an M.S. and Ph.D. in Computer Science from Carnegie Mellon University, and a B.Tech. in Computer Science and Engineering from the Indian Institute of Technology, Bombay. His research interests are in dependable computing and computational logic, with a current focus on applying automated formal methods to problems in embedded systems, electronic design automation, computer security, and program analysis. His Ph.D. thesis work on the UCLID verifier and decision procedure helped pioneer the area of satisfiability modulo theories (SMT) and SMT-based verification. He is co-author of a widely-used textbook on embedded systems. His awards and honors include a Presidential Early Career Award for Scientists and Engineers (PECASE) from the White House, an Alfred P. Sloan Research Fellowship, and the School of Computer Science Distinguished Dissertation Award at Carnegie Mellon University.

Mohammad A. Al Faruque
University of California, Irvine

Functional-Level Design Space Exploration of the Multi-domain Cyber-Physical Systems

Abstract

Mohammad Abdullah Al Faruque is currently with University of California Irvine (UCI), where he is a tenure track assistant professor and directing the Emulex Career Development Chair and the cyber-physical systems lab. Before, he was with Siemens Corporate Research and Technology in Princeton, NJ. His current research is focused on system-level design of embedded systems and/or Cyber-Physical-Systems (CPS) with special interest on model-based design of software-integrated (multi)-physics systems, multi-core systems, real-time scheduling algorithms, etc.

Siddharth Garg
University of Waterloo

Reliable Computing in the Dark/Dim Silicon Era

Abstract

Siddharth Garg is Assistant Professor in the Electrical and Computer Engineering Department at NYU. He received a Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University in 2009 and a Bachelor's degree in Electrical Engineering from the Indian Institute of Technology Madras (IIT-M) in 2004.

Garg’s research interests are in the areas of energy-efficient, reliable and secure computing hardware with interests spanning from emerging device technologies to electronic design automation (EDA) and computer architecture. He has authored or co-authored more than 40 papers in reputed journals and conferences, and serves on the technical program committees of several major conferences.

Garg’s research has been recognized with best paper awards at the 2013 Usenix Security Symposium and the 2009 International Symposium on Quality in Electronic Design (ISQED), and with the Angel Jordan award for outstanding thesis contributions from the ECE Department at Carnegie Mellon University. Prior to coming to NYU, Garg was an Assistant Professor at the University of Waterloo for four years.

Akash Kumar
National University of Singapore

Improving FPGA Design Reliability Using Embedded Hamming Scheme

Abstract

He received the B.Eng. degree in computer engineering from the National University of Singapore (NUS), Singapore, in 2002. He received the joint Master of Technological Design degree in embedded systems from NUS and the Eindhoven University of Technology (TUe), Eindhoven, The Netherlands, in 2004, and the joint Ph.D. degree in electrical engineering in the area of embedded systems from TUe and NUS, in 2009. His thesis is entitled Analysis, Design and Management of Multimedia Multiprocessor Systems. In 2004, he was with Philips Research Labs, Eindhoven, The Netherlands, where he worked on Reed Solomon codes as a Research Intern. From 2005 to 2009, he was with TUe as a Ph.D. student under project PreMaDoNA. Since 2009, he has been with the Department of Electrical and Computer Engineering, NUS, where he is currently employed as an Assistant Professor. He has published over 70 papers in leading international electronic design automation journals and conferences. His research interests are in design, analysis and resource management of predictable, reliable and low-power multi-processor systems. He is a member of various technical program committee of design automation and FPGA conferences like DAC, DATE, FPL and FPT.

Kyoungwoo Lee
Yonsei University

Software-based Selective Voting for Dependable Coarse-Grained Reconfigurable Architectures against Soft Errors

Kyoungwoo Lee is Assistant Professor in the Department of Computer Science and Engineering at Yonsei University, Seoul, South Korea. He has received his Ph.D. in Information and Computer Science from University of California, Irvine, and masters and bachelors in Computer Science from Yonsei University. He was with LG Electronics, Inc., for 6 years where he has been involved with several industrial projects such as home networking Digital TV/STB. His research is in the area of embedded systems, with a specific focus on cross-layer design and optimization for error-aware and energy-efficient embedded systems.

Karthik Pattabiraman
University of British Columbia

LLFI: A High-Level Fault Injection Framework for Evaluating Software Error Resilience Techniques

Abstract

Karthik Pattabiraman received his M.S and PhD. degrees from the University of Illinois at Urbana-Champaign (UIUC) in 2004 and 2009 respectively. After a post-doctoral stint at Microsoft Research (Redmond), Karthik joined the University of British Columbia (UBC) as an assistant professor of electrical and computer engineering. Karthik's research interests include programming languages, compilers and computer architecture for building error resilient software systems. Karthik has won a best paper award at the IEEE International Conference on Dependable Systems and Networks (DSN), 2008, a best paper runner up award at the IEEE International Conference on Software Testing (ICST), 2013 and a Distinguished paper award at the IEEE/ACM International Conference on Software Engineering (ICSE), 2014. Karthik was recently the general chair for the IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), 2013.

Rishad Shafik
University of Southhampton

Runtime Management of Energy-Efficient and Reliable Many-Core Systems

Abstract

Dr. Rishad Ahmed Shafik is currently working as a senior research fellow in the School of Electronics and Computer Science (ECS), University of Southampton, UK. His current research interests include energy-efficient and reliable design techniques and programming models for many-core systems within the remits of PRiME project, funded by EPSRC programme grant scheme (www.prime-project.org). Before joining the University of Southampton, he has worked as an EU research fellow in the University of Bristol, UK from 2011 to 2013. Prior to that he has also served as an Assistant Professor in the Islamic University of Technology (IUT, a subsidiary organ of the OIC in Bangladesh) from 2002 to 2006. Dr. Rishad received the PhD and MSc (with distinction) degrees from the University of Southampton in 2010 and 2005, and BSc in Electronic Engineering degree (with distinction) from the Islamic University of Technology (IUT), Bangladesh in 2001. Dr. Rishad is one of the editors of the book, “Energy-Efficient Fault-Tolerant Systems," published by Springer USA; recently authored two other monographs on multimedia and implantable systems design. He has also authored 50+ research articles in various international journals and conferences. Dr. Rishad is a member of IEEE and IET.

Muhammad Shafique
Karlsruher Institut für Technologie

Hardware-Software Cooperative Reliability Boosting in the Dark Silicon Era

Dr. Muhammad Shafique is a research group leader and lecturer at the Chair for Embedded Systems (CES), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. He has 10+ years' research and development experience in power-/performance-efficient embedded systems in leading industrial and research organizations. Dr. Shafique received his Ph.D. in Computer Science from Karlsruhe Institute of Technology (KIT), Germany in January 2011. Before, he was with Streaming Networks Pvt. Ltd. and WorldCall Multimedia Pvt. Ltd. He received his B.Sc. Engineering from UET Lahore, Pakistan (with 4 Gold Medals) and Masters in Information Technology from PIEAS, Pakistan (with 2 Gold Medals) in 2000 and 2003, respectively. His main research interests are algorithms, architectures, and design methodologies for embedded systems with a focus on low-power and reliability. Dr. Shafique holds one US patent, 6 Gold Medals, DAC'14 Designer Track Best Poster Award, CODES+ISSS'11 Best Paper Award, DATE'08 Best Paper Award, AHS'11 Best Paper Award, CODES+ISSS'14 Best Paper Nomination, ICCAD'10 Best Paper Nomination, several HiPEAC Paper Awards between 2008 and 2014, and Best Master's Thesis Award. He is a member of IEEE and IEEE Signal Processing Society (SPS). He has (co)-authored 2 books and 90+ publications in premier conferences and journals on various aspects of low-power, reliable, and adaptive embedded systems. He has given multiple tutorials in the area of embedded systems and organized several special sessions and a workshop at premier conferences. Dr. Shafique has also served as a technical program committee member of various premier IEE/ACM conferences including ICCAD, DATE, CASES, ASP-DAC, ESTIMedia, etc.

Aviral Shrivastava
Arizona State University

Control Flow Checking or Not? (for Soft Errors)

Abstract

Prof. Aviral Shrivastava is Associate Professor in the School of Computing Informatics and Decision Systems Engineering at the Arizona State University. He received his Ph.D. and Masters in Information and Computer Science from University of California, Irvine, and bachelors in Computer Science and Engineering from Indian Institute of Technology, Delhi. He is the recipient of 2010 NSF CAREER Award, 2011 Outstanding Junior Researcher in CSE at ASU, and the second most prolific author in ESWEEK in the last 5 years. His research lies at the intersection of compilers and architectures of embedded and multi-core systems, with the goal of improving power, performance, and reliability. His research is funded by NSF, DOE, and several industries including Microsoft, Raytheon Missile Systems, Intel, Nvidia, Toyota Motor Company. He serves on organizing and program committees of several premier embedded system conferences, including DAC, ISLPED, CODES+ISSS, CASES and LCTES, and regularly serves on NSF and DOE review panels.

Joseph Sloan
University of Texas at Dallas

Algorithm Selection for Error Resilience in Scientific Computing

With process scaling and the adoption of post-cmos technologies, reliability and power are becoming a significant concern for future computing systems, especially highly parallel systems. Previous approaches have investigated augmenting applications with additional logic to detect and correct errors efficiently. In this research, we investigate the impact of different algorithmic designs on error resilience and propose an approach for algorithm selection for a class of equations, i.e. partial differential equations (PDEs), that are at the core of many scientific computing applications, which drive HPC systems. Many different schemes have been devised for the approximation of PDE systems, each with different accuracy, stability, and performance properties. In this research, there are two primary questions that we address: (1) Does numerical stability translate to error resilience? and (2) How do we design schemes to improve error resilience? If an algorithm’s error resilience is correlated with its numerical stability properties, this may allow us to design more resilient applications by leveraging well established information on numerical stability. Even with a clear translation of numerical stability to error resilience properties, the question of designing these algorithms still remains however, due to the variety of implementations, schemes, and largely input specific nature of the design. In this research, we propose one approach for automated design using machine-learning. We observe that intelligent selection of the algorithm or a given problem, improves robustness by 20%-50%, on average, over the traditional selection of algorithms, without the addition of any other detection/correction logic.

Joseph Sloan is an Assistant Professor in the Electrical Engineering Department at the University of Texas at Dallas. He received a B.S. degree in electrical engineering and a B.S. degree in computer engineering from Iowa State University in 2007, and his M.S. and Ph.D degrees in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 2011 and 2013, respectively. His research interests include fault-tolerant computing, high performance and scientific computing, computer architecture, and low-power design. Joseph’s research has been recognized by the Yi-MinWang and Pi-Yu Chung Endowed Research Award, a Best Paper in Session Award at SRC TECHCON 2011, a 2012 ECE/Intel Computer Engineering Fellowship, and and has been the subject of several keynote talks, invited plenary lectures, and invited articles. His research also forms a core component of 2010 NSF Expedition in Computing Award and has been covered by media sources, including BBC News, IEEE Spectrum, and HPCWire.

Chengmo Yang
University of Delaware

Compiler-directed Selective Register Checkpointing

Abstract

Chengmo Yang received the B.S. degree in microelectronics from Peking University, Beijing, China, in 2003, and the M.S. and Ph.D. degrees in computer engineering from the University of California at San Diego, La Jolla, CA, USA, in 2005 and 2010, respectively. She is currently an Assistant Professor with the Department of Electrical and Computer Engineering, University of Delaware, Newark, DE, USA. Her research interests include fault resilience, hardware support for system security, multi/many-core architectures, embedded system design, compile-time and run-time optimizations, scheduling and resource management, and nonvolatile memories. She was a recipient of the University of Delaware Research Foundation Award and the National Science Foundation CAREER Award.